Image: Circuit Board, Free Stock Picture,

iPhone 14 Pro chip bigger despite smaller transistors

Image: Circuit Board, Free Stock Picture,
Closeup of old circuit board. Image: Circuit Board, Free Stock Picture,

Small changes to caches and processor cores, this is how a preliminary analysis of the A16 silicon chip  from Angstronomics can be summarized. Although there is still no high-resolution image of the die, there is a video in which some details can already be seen. Since various components such as caches, processors and GPU form unique patterns on the die, they can be identified and at least roughly measured.

The operator of Angstronomics, who publishes under the pseudonym Skyjuice, comes to the conclusion that Apple has reduced the L3 or system level cache (SLC) in the A16 compared to the predecessor A15. Compared to the 4 MB L2 cache of the Efficiency CPU cluster made of Sawtooth cores, each of the two SLC blocks occupies about three times the area, so it should hold 12 MB – the SRAM memory cells need the same regardless of the cache hierarchy lots of space.

This means that the SLC of the A16, at 24 MB, is a quarter smaller than that of the A15, which has 32 MB. However, Apple has given the performance cores named Everest a third more L2 cache: the area here suggests that each of the two blocks holds 8 MB, while the A15 had a total of 12 MB.

One can only speculate about the reason for the reduction of the size of the SLC: Angronomics brings the higher data rate of the memory into play as a possible reason: LPDDR5-6400 is used for the first time in the A16. Optimizations are also conceivable, since the L2 cache of the P-cores was enlarged at the same time. Many factors play a role in the dimension of caches, including the micro architecture of the processors – it is very likely that there was not a single decisive argument for the redistribution.

Changes to processor cores

There are also small changes in the processor cores: they are arranged differently on the die, and Apple has also revised their structure. Both the Everest and Sawtooth (P/E) cores also appear to be slightly larger than their Avalanche and Blizzard predecessors. The neural and graphics processing units (NPU and GPU), on the other hand, seem to be quite unchanged. However, they are hardly recognizable in the Angtronomics image.

However, the NPU is only eight percent faster than the A15. This is part of the switch from the supplier TSMC from the N5 to the N4 process and the expected increase in speed of ten percent as a result. Major changes are therefore unlikely. The higher switching speed of the transistors in N4 should also play a role in the GPU, which also benefits from the larger memory bandwidth. Together, both could almost explain the measured 28 percent increase in speed .

Bigger chip despite (slightly) smaller transistors

With N4, TSMC refers to a further development of the N5 manufacturing process, with which Apple’s A15 is manufactured. According to TSMC, this increases the integration density by six percent, and the number of transistors also increases by six percent – ​​16 billion in the A16, 15 billion in the A15. Theoretically, the dies of A15 and A16 could be the same size.